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1 for more information www.linear.com/LTC7130 typical application features description the lt c ? 7130 is a current mode synchronous step- down monolithic converter that can deliver up to 20 a continuous load current. it employs a unique architecture which enhances the signal- to- noise ratio of the current sense signal, allow - ing the use of a very low dc resistance power inductor to maximize efficiency in high current applications. this feature also reduces the switching jitter commonly found in low dcr applications. the LTC7130 also includes a high speed differential remote sense amplifier and a programmable cur - rent sense limit that can be selected from 10mv to 30mv to set the output current limit up to 20a . in addition, the dcr temperature compensation feature limits the maximum output current precisely over temperature. the LTC7130 also features a precise 0.6 v reference with a guaranteed limit of 0.5% that provides an accurate output voltage. a 5 v to 20 v input voltage range supports a wide variety of bus voltages and various types of batteries. the LTC7130 is offered in a compact and low profile bga pack - age available with snpb/ rohs compliant terminal finishes. applications n wide v in range: 4.5v to 20v n optimized for low duty cycle applications n high effciency: up to 95% n ltc proprietary current mode architecture n high current parallel operation n ultralow dcr current sensing with temperature?compensation n programmable output current limit n high speed differential remote sense amplifer n 0.5% output voltage regulation accuracy n output short-circuit protection with soft recovery n programmable soft-start, tracking n programmable fixed frequency: 250khz to 770khz n extv cc for reduced power dissipation n fault indicator for output uv/ov conditions n 6.25mm 7.5mm 2.22mm bga package n dsp, fpga, asic reference designs n telecom/datacom systems n distributed high power density systems l , lt , lt c , lt m , burst mode, opti - loop, module, linear technology and the linear logo are registered trademarks and no r sense is a trademark of analog devices, inc. all other trademarks are the property of their respective owners. protected by u.s . patents, including 5481178, 5705919, 5929620, 6177787, 6580258, 6498466, 6611131, patent pending. high efficiency, 1.5v/20a step-down converter with very low dcr sensing efficiency vs load current 20v 20a monolithic buck converter with ultralow dcr sensing + + ltc 7130 7130fb 0 2 4 6 8 10 12 14 16 18 efficiency 20 0 10 20 30 40 50 60 70 80 power loss 90 100 0 2 4 6 8 10 12 14 v in = 12v efficiency (%) power loss (w) 7130 ta01b 20k cmdsh2-3 0.1f 0.25h (0.37m dcr) 3.09k 220nf 619 v out = 1.5v 4.7f 1f 2.2 121k 470f 2 220pf 470f 20k 30.1k 1nf l = 0.25h (dcr = 0.37m) intv cc tk/ss ith gnd svin freq sns ? snsa + snsd + sw extv cc = 5v boost ilim LTC7130 diffn diffp mode/pllin diffout v fb v out 1.5v 20a itemp ccm sgnd run v in v in = 5v to 20v pins not used in this circuit: pgood clkout extv cc 220nf 0.1f load current (a) intv cc 3.01k 1k 2.2 7130 ta01a
2 for more information www.linear.com/LTC7130 absolute maximum ratings input supply voltage .................................. C 0.3 v to 20 v extv cc , run , pgood ................................. C 0.3 v to 6v snsd + , snsa + , sns C voltages ............. C 0.3 v to intv cc mode / pllin , ilim , tk / ss , freq ......... C 0.3 v to intv cc diffp , diffn ......................................... C0. 3 v to intv cc itemp , ith , v fb voltages ...................... C 0.3 v to intv cc operating junction temperature range ( note 2) .................................................. C 40 c to 125 c storage temperature range .................. C 65 c to 150 c peak solder reflow body temperature ................. 260 c (note 1) electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, v run = 5v unless otherwise specified. symbol parameter conditions min typ max units main control loops v in input voltage range (note 3) 4.5 20 v v out output voltage range with diffamp low dcr sensing without diffamp and no low dcr sensing 0.6 0.6 3.5 5.5 v v v fb regulated feedback voltage current ith voltage = 1.2v (note 4) C40c to 85c C40c to 125c l l 0.597 0.5955 0.6 0.6 0.603 0.6045 v v 1 a b c d e f g h j 2 3 4 top view bga package 63-pin (6.25mm 7.5mm 2.22mm) 5 6 7 v in sw intv cc gnd gnd boost sgnd nc1 nc2 diffn diffp diffout ith v fb snsd + freq sns ? tk/ss run snsa + itemp ilim clkout mode/ pllin sv in extv cc pgood t jmax = 125c, e ja = 21c/w, e jc = 10c/w e ja derived from LTC7130 demo board, weight = 0.24g pin configuration part number pad or ball finish part marking* package type msl ra ting temperature range (see note 2) device finish code LTC7130ey#pbf sac305 (rohs) LTC7130 e1 bga 3 C40c to 125c LTC7130iy#pbf sac305 (rohs) LTC7130 e1 bga 3 C40c to 125c ? device temperature grade is indicated by a label on the shipping container. ? pad or ball finish code is per ipc/jedec j-std-609. ? terminal finish part marking: www.linear.com/leadfree ? this product is not recommended for second side reflow. for more information, go to www.linear.com/bga-assy ? recommended bga pcb assembly and manufacturing procedures: www.linear.com/bga-assy ? bga package and t ray drawings: www.linear.com/packaging ? this product is moisture sensitive. for more information, go to: www.linear.com/bga-assy order information (http://www .linear.com/product/LTC7130#orderinfo) ltc 7130 7130fb
3 for more information www.linear.com/LTC7130 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, v run = 5v unless otherwise specified. symbol parameter conditions min typ max units i fb feedback current (note 4) C15 C50 na v reflnreg reference voltage line regulation v in = 4.5v to 20v (note 4) 0.002 0.02 % v loadreg output voltage load regulation (note 4) measured in servo loop; ? ith voltage = 1.2v to 0.7v measured in servo loop; ? ith voltage = 1.2v to 1.6v l l 0.01 0.01 0.1 0.1 % % g m error amplifier (ea) transconductance ith =1.2v, sink/source 5a (note 4) 2 mmho i q input dc supply current normal mode shutdown ( note 5) v run = 0v 3.8 30 50 ma a uvlo undervoltage lockout v intvcc ramping down 3.4 3.75 4.1 v uvlo hys uvlo hysteresis voltage 0.5 v v fbovl feedback overvoltage lockout measured at v fb l 0.64 0.66 0.68 v i snsd + snsd + pin bias current v snsd + = 3.3v 30 100 na i snsa + snsa + pin bias current v snsa + = 3.3v 1 2 a a vt_sns total sense signal gain to current comparator 5 v/v v sense(max) maximum current sense threshold C40c to 125c v sns C = 1.8v, i lim = 0v i lim = 1/4v intvcc i lim = 1/2v intvcc or float i lim = 3/4v intvcc i lim = v intvcc l l l l l 8.8 14 19 23.5 28.3 10 15 20 25 30 11.2 16 21 26.5 31.7 mv mv mv mv mv i temp dcr temperature compensation current v itemp = 0.3v l 9 10 11 a i tk/ss soft-start charge current v tk/ss = 0v l 1.0 1.25 1.5 a v run run pin on threshold voltage v run rising l 1.1 1.22 1.35 v v run(hys) run pin on hysteresis voltage 80 mv t on(min) minimum on-time (note 6) 90 ns intv cc linear regulator v intvcc internal v cc voltage 6v < v in < 20v 5.25 5.5 5.75 v load regulation i intvcc = 0ma to 20ma 0.5 2 % v extvcc external v cc switchover voltage extv cc ramping positive 4.5 4.7 v extv cc voltage drop i extvcc = 20ma, v extvcc = 5.5v 40 100 mv extv cc hysteresis 250 mv oscillator and phase-locked loop f nom nominal frequency v freq = 1.2v 450 500 550 khz f low lowest frequency v freq = 0.4v 225 250 275 khz f high highest frequency v freq > 2.4v 700 770 850 khz r mode/pllin mode/pllin input resistance 250 k i freq frequency setting current 9 10 11 a ltc 7130 7130fb
4 for more information www.linear.com/LTC7130 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, v run = 5v unless otherwise specified. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC7130 is tested under pulsed load conditions such that t j t a . the LTC7130e is guaranteed to meet performance specifications from 0c to 85c operating junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC7130i is guaranteed to meet performance specifications over the full C40c to 125c operating junction temperature range. the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the package thermal impedance and other environmental factors. the thermal derating curves are based on the LTC7130 demo board. symbol parameter conditions min typ max units clkout phase relative to the oscillator clock 180 deg clkout hi clock output high voltage v intvcc = 5.5v 4.5 5.5 v clkout lo clock output low voltage 0 0.2 v pgood output v pgdlo pgood voltage low i pgood = 2ma 0.1 0.3 v i pgd pgood leakage current v pgood = 5.5v 2 a v pgd pgood trip v fb with respect to set output voltage v fb going negative v fb going positive C10 10 % % differential amplifier a v gain C40c to 125c l 0.997 1 1.003 v/v r in input resistance measured at diffp input 80 k v os input offset voltage v diffp = 1.5v, v diffout = 100a 2 mv psrr power supply rejection ratio 5v < v in < 20v (note 7) 90 db i out maximum sourcing output current 1.5 2 ma v out maximum output voltage v intvcc = 5.5v, i diffout = 300a v intvcc C 1.4 v intvcc C 1.1 v gbw gain-bandwidth product (note 7) 3 mhz sr slew rate (note 7) 2 v/s r ds(on) r top top power nmos on- resistance 7.3 m? r bottom bottom power nmos on- resistance 2.1 m? note 3: when 4.5v v in 5.5v, intv cc must be tied to v in . guaranteed by design. note 4: the LTC7130 is tested in a feedback loop that servos v ith to a specified voltage and measures the resultant v fb . note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: the minimum on-time condition corresponds to the on inductor peak-to-peak ripple current 40% of i max (see minimum on-time considerations in the applications information section). note 7: guaranteed by design. ltc 7130 7130fb
5 for more information www.linear.com/LTC7130 load step (burst mode ? operation) inductor current at light load load step (continuous conduction mode) prebiased output at 1v load step (pulse-skipping mode) typical performance characteristics t a = 25c, unless otherwise noted. efficiency vs load current and mode efficiency vs load current and mode efficiency vs load current and mode efficiency and power loss vs load current ltc 7130 7130fb 9 70 80 90 100 efficiency (%) f sw = 500khz out l = 0.25h (dcr = 0.37m) front page circuit ccm 11 burst mode operation pulse?skipping mode v = 1.5v 3681 g01 v in = 5v load current (a) 0.1 1 10 100 14 0 10 20 30 40 50 60 70 80 90 17 100 efficiency (%) f sw = 500khz out l = 0.25h (dcr = 0.37m) front page circuit ccm burst mode operation pulse?skipping mode v = 1.5v 20 3681 g02 v in = 12v load current (a) 0.1 1 10 100 0 10 20 0 30 40 50 60 70 80 90 100 efficiency (%) f sw = 400khz 10 out l = 0.25h (dcr = 0.37m) front page circuit extv cc = 5v ccm burst mode operation pulse?skipping mode v = 1v 3681 g03 v in = 12v 20 load current (a) 30 40 v in = 20v 50 60 70 80 90 100 0 5 10 15 efficiency efficiency (%) power loss (w) vs load current 7130 g04 (burst mode operation) v in = 12v v out = 1.5v front page circuit 20s/div i load power loss 5a/div 1a to 15a v out ac?coupled 100mv/div 7130 g05 v in = 12v v out = 1.5v front page circuit 20s/div v out = 1.5v v out ac?coupled 100mv/div i load 5a/div 1a to 15a 7130 g06 v in = 12v v out = 1.5v front page circuit load current (a) 20s/div i load 5a/div 1a to 15a v out ac?coupled 100mv/div 7130 g07 v in = 12v v out = 1.5v 0 load = 300ma 10s/div pulse?skip mode 10a/div burst mode operation 10a/div continuous conduction mode 10a/div 7130 g08 3 v in = 12v v out = 1.5v track/ss 500mv/div 20ms/div v fb 500mv/div v out 500mv/div 7130 g09 0.1 6 1 10 100 0 10 20 30 40 50 60
6 for more information www.linear.com/LTC7130 intv cc line regulation current sense threshold vs ith voltage maximum current sense threshold vs common mode voltage v ith (v) 0 ?10 current sense threshold (mv) ?5 5 10 15 40 25 0.5 1.0 1.25 7130 g12 0 30 35 20 0.25 0.75 1.5 1.75 2.0 i lim = 0v i lim = 1/4 intv cc i lim = 1/2 intv cc i lim = 3/4 intv cc i lim = intv cc v sense common mode voltage (v) 0 current sense threshold (mv) 20 30 4.0 7130 g13 10 0 1.0 2.0 3.0 0.5 1.5 2.5 3.5 40 15 25 5 35 i lim = intv cc i lim = 0v i lim = 3/4 intv cc i lim = 1/4 intv cc i lim = 1/2 intv cc typical performance characteristics t a = 25c, unless otherwise noted. shutdown (run) threshold vs temperature regulated feedback voltage vs temperature oscillator frequency vs temperature tk/ss pull-up current vs temperature maximum current sense threshold voltage vs feedback voltage (current foldback) feedback voltage (v) 0 maximum current sense threshold (mv) 15 20 25 0.3 0.5 7130 g14 10 5 0 0.1 0.2 0.4 30 35 40 0.6 i lim = intv cc i lim = 3/4 intv cc i lim = 1/2 intv cc i lim = 1/4 intv cc i lim = 0v temperature (c) tk/ss (a) 7130 g15 temperature (c) run threshold (v) 7130 g16 1.00 1.20 1.30 1.10 1.40 1.15 1.25 1.05 1.35 on off temperature (c) 598.5 regulated feedback voltage (mv) 599.0 599.5 600.0 600.5 7130 g17 601.0 601.5 temperature (c) frequency (khz) 7130 g18 500 550 450 400 600 475 525 425 575 v freq = 1.2v tracking up and down with tk / ss external ramp v tk/ss 0.2v/div v out 0.5v/div 20ms/div 7130 g10 v in = 12v v out = 1.5v 1 load 0v v tk/ss v out ltc 7130 7130fb 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 ?50 ?50 ?25 0 25 50 75 100 125 ?50 ?25 ?25 0 25 50 75 100 125 ?50 ?25 0 25 0 50 75 100 125 input voltage (v) 0 5 10 15 20 25 0 1 2 4 5 6 intv cc voltage (v) cc 7130 g11 50 75 100 125
7 for more information www.linear.com/LTC7130 oscillator frequency vs input voltage v freq = 2.5v v freq = 1.2v v freq = 0v frequency (khz) 500 600 700 400 300 0 200 100 900 800 7130 g19 input voltage (v) typical performance characteristics undervoltage lockout threshold (intv cc ) vs temperature shutdown current vs input voltage t a = 25c, unless otherwise noted. temperature (c) 2.5 uvlo threshold (v) 2.7 3.1 3.3 3.5 4.5 3.9 7130 g20 2.9 4.1 4.3 3.7 rise fall input voltage (v) 0 shutdown current (a) 10 30 40 50 100 70 7130 g21 20 80 90 60 shutdown current vs temperature input quiescent current vs input voltage without extv cc quiescent current vs temperature without extv cc temperature (c) shutdown current (a) 30 40 7130 g22 20 10 50 25 35 15 45 input voltage (v) 7130 g23 quiescent current (ma) 3.50 3.75 4.00 3.25 3.00 2.75 2.50 temperature (c) 7130 g24 quiescent current (ma) 3.2 3.6 2.8 2.4 4.0 3.0 3.4 2.6 3.8 thermal derating v in = 5v thermal derating v in = 12v thermal derating v in = 20v ltc 7130 7130fb 25 125 0 5 10 15 20 25 maximum load current (a) thermal derating vin = 20v 7130 g27 50 75 100 125 0 5 10 15 20 0 ?50 ?25 0 25 50 75 100 125 0 5 5 10 15 20 ?50 ?25 0 25 50 75 100 10 125 v out = 1.5v f sw = 500khz dc2341a demo board no heat sink 0lfm 200lfm 400lfm ambient temperature (c) 0 15 25 50 75 100 125 0 5 10 15 20 20 25 maximum load current (a) thermal derating vin = 5v 7130 g25 v out = 1.5v f sw = 500khz dc2341a demo board no heat sink 0lfm 200lfm ?50 400lfm ambient temperature (c) 0 25 50 75 100 125 0 5 ?25 10 15 20 25 maximum load current (a) thermal derating vin = 12v 7130 g26 v out = 1.5v f sw = 500khz dc2341a demo board 0 no heat sink 0lfm 200lfm 400lfm ambient temperature (c) 0 25 50 75 100
8 for more information www.linear.com/LTC7130 pin functions freq (b7): oscillator frequency control input. a 10a current source flows out of this pin. connecting a resistor between this pin and ground sets a dc voltage which in turn programs the oscillator frequency. alternatively, this pin can be driven with a dc voltage to vary the frequency of the internal oscillator. run (b6): run control input. a voltage above 1.22v turns on the ic. pulling this pin below 1.1 v causes the ic to shut down. there is a 1 a pull-up current for the pin. once the run pin rises above 1.22 v, an additional 4.5a pull-up current is added to the pin. tk/ss (b5): output voltage tracking and soft-start input. an internal soft- start current of 1.25 a charges the external soft-start capacitor connected to this pin. ith (a5): current control threshold and error ampli - fier compensation pin. the current comparator tripping threshold is proportional with this voltage. v fb (a6): error amplifier feedback input. this pin receives the remotely sensed feedback voltage to set the output voltage through an external resistive divider connected to the diffout pin or the output. diffout (a4): output of remote sensing differential amplifier. connect this pin to v fb through a resistive divider to set the desired output voltage. diffn (a2): negative input of remote sensing differen - tial amplifier. connect this pin close to the ground of the output load. diffp (a3): positive input of remote sensing differential amplifier. connect this pin close to the output load. snsd + (b1): dc current sense comparator input. the (+) output to the dc current. comparator is normally connected to a dc current sensing network with a time constant that matches the bandwidth, l/dcr, of the inductor. sns C (b2): negative current sense input. this negative input of the current comparator is to be connected to the output. snsa + (c1): ac current sense comparator input. the?(+) output to the ac current comparator is normally connected to a dcr sensing network. when combined with the snsd + pin, the dcr sensing network can be skewed to increase the ac ripple voltage by a factor of 5. ilim (c2): current comparator sense voltage limit. apply a dc voltage to set the maximum current sense threshold for the current comparator. clkout (c3): clock output pin. the clkout signal is 180 out of phase to the rising edge of the ic internal clock . gnd ( d2, d3, d4, e1, e2, e3, f2, f3, g4, g5, g6, h4, h5, h6, h7, j4, j5, j6, j7): power ground. connect this pin closely to the ( C) terminal of cv cc and the (C) terminal of c in . sw ( g1, g2, g3, h1, h2, h3, j1, j2, j3): switch node connection. connect this pin to the output filter induc - tor, bottom n-channel mosfet drain and top n-channel mosfet source. voltage swing at these pins is from a schottky diode ( external) voltage drop below ground to v in . boost (f1): boosted top gate driver supply. the (+) terminal of the bootstrap capacitor connects to this pin. this pin swings from a diode voltage drop below intv cc up to v in + intv cc . intv cc (d1): internal 5.5 v regulator output. the internal control circuits are powered from this voltage. decouple this pin to pgnd with a 4.7 f low esr tantalum or ce - ramic capacitor. ltc 7130 7130fb
9 for more information www.linear.com/LTC7130 pin functions sv in (d5): main input supply. decouple this pin to pgnd with a capacitor (0.1 f to 1 f). for applications where the main input power is 5 v, tie the sv in and intv cc pins together. v in ( e4, e5, e6, e7, f4, f5, f6, f7, g7): main input supply. these pins connect to the drain of the internal power mosfets. decouple this pin to gnd with the input capacitance c in . extv cc ( d7): external supply voltage input. whenever an external voltage supply greater than 4.7 v is connected to this pin, an internal switch will close and bypass the internal low dropout regulator, and the external supply will power the ic. do not exceed 6 v on this pin and ensure v in > v extvcc at all times. itemp (d6): temperature dcr compensation input. con- nect to a ntc ( negative tempco) resistor placed near the output inductor to compensate for its dcr change over temperature. floating this pin or tying it to intv cc disables the dcr temperature compensation function. pgood (c7): power good indicator output. open-drain logic out that is pulled to ground when the output exceeds the 10% regulation window, after the internal 20 s power bad mask timer expires. mode /pllin (c6): mode operation or external clock synchronization. connect this pin to sgnd to set the continuous mode of operation. connect to intv cc to en- able pulse -skipping mode of operation. leaving the pin floating will enable burst mode operation. a clock signal applied to the pin will force the controller into continuous mode of operation and synchronizes the internal oscillator. sgnd ( b3, b4, c4, c5): signal ground. this is the ground of the controller. connect compensation components and output setting resistors to this ground. nc ( a1, a7): do not connect. these pins are not connected to anything internally. ltc 7130 7130fb
10 for more information www.linear.com/LTC7130 functional block diagram ? + ? ++ sleep intv cc 0.55v ? + ? + 0.5v ss ? + 1.22v run 1.25a v in ea ith run tk/ss 0.6v ref s r q 5.5v reg active clamp osc mode/sync detect slope compensation uvlo 1 r i thb 1a/5.5a freq clkout mode/pllin itemp 0.6v burst en extv cc ilim ? + ? + i comp i rev f ? + 4.7v f ? + ? + ov uv ? + diffamp ? + amp 0.54v v fb pgood gnd c b v out v in c out d b sns ? snsa + sw boost intv cc diffn diffp snsd + 7130 bd sgnd 0.66v 40k 40k 40k 40k switch logic and antishoot- through ov run on fcnt pll-sync tempsns + c in + sv in v sns ? c vcc intv cc r c c c1 c ss diffout ra rb ltc 7130 7130fb
11 for more information www.linear.com/LTC7130 operation main control loop the LTC7130 uses a lt c proprietary current sensing, current mode step- down architecture. during normal operation, the top mosfet is turned on every cycle when the oscillator sets the rs latch, and turned off when the main current comparator, i cmp , resets the rs latch. the peak inductor current at which i cmp resets the rs latch is controlled by the voltage on the ith pin, which is the output of the error amplifier, ea. the remote sense ampli - fier ( diffamp) produces a signal equal to the differential voltage sensed across the output capacitor divided down by the feedback divider and re-references it to the local ic ground reference. the v fb pin receives this feedback signal and compares it to the internal 0.6 v reference. when the load current increases, it causes a slight decrease in the v fb pin voltage relative to the 0.6 v reference, which in turn causes the ith voltage to increase until the inductors average current equals the new load current. after the top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator, i rev , or the beginning of the next cycle. the main control loop is shut down by pulling the run pin low. releasing run allows an internal 1.0 a current source to pull up the run pin. when the run pin reaches 1.22v, the main control loop is enabled and the ic is powered up. when the run pin is low, all functions are kept in a controlled state. sensing signal of very low dcr the LTC7130 employs a unique architecture to enhance the signal-to-noise ratio that enables it to operate with a small sense signal of a very low value inductor dcr , 1m or less, to improve power efficiency, and reduce jitter due to the switching noise which could corrupt the signal. the LTC7130 comprises two positive sense pins, snsd + and snsa + , to acquire signals and processes them internally to provide the response as with a dcr sense signal that has a 14db signal-to-noise ratio improvement. in the meantime, the current limit threshold is still a function of the inductor peak current and its dcr value, and can be accurately set from 10 mv to 30 mv in a 5 mv steps with the ilim pin. the filter time constant, r1???c1, of the snsd + should match the l/dcr of the output inductor, while the filter at snsa + should have a bandwidth of five times larger than snsd + , r2???c2 equals r1?? c1/5 (see figure 3). intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is tied to a voltage less than 4.7v, an internal 5.5 v linear regulator supplies intv cc power from v in . ground extv cc if it is not used. if extv cc is taken above 4.7 v, the 5.5 v regulator is turned off and an internal switch is turned on connecting extv cc to intv cc . using the extv cc pin allows the intv cc power to be derived from a high efficiency external source such as a switch- ing regulator output. the top mosfet driver is biased from the floating bootstrap capacitor, c b , which normally recharges during the off cycle through an external diode when the top mosfet turns off. if the input voltage, v in , decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continu- ously. the dropout detector detects this and forces the top mosfet off for about one-twelfth of the clock period plus 100ns every third cycle to allow c b to recharge (note 7). however, it is recommended that a load be present or the ic operates at low frequency during the dropout transition to ensure c b is recharged. internal soft-start by default, the start-up of the output voltage is normally controlled by an internal soft-start ramp. the internal soft-start ramp connects to the noninverting input of the error amplifier. the v fb pin is regulated to the lower of the error amplifiers three noninverting inputs ( the inter- nal soft -start ramp, the tk/ss pin or the internal 600mv reference). as the ramp voltage rises from 0 v to 0.6 v over approximately 600 s, the output voltage rises smoothly from its prebiased value to its final set value. certain applications can result in the start-up of the con - verter into a non-zero load voltage, where residual charge is stored on the output capacitor at the onset of converter switching. in order to prevent the output from discharging under these conditions, the bottom mosfet is disabled until soft-start is greater than v fb . ltc 7130 7130fb
12 for more information www.linear.com/LTC7130 shutdown and start-up (run and tk/ss pins) the LTC7130 can be shut down using the run pin. pulling the run pin below 1.1 v shuts down the main control loop for the controller and most internal circuits, including the intv cc regulator. releasing the run pin allows an internal 1.0a current to pull up the pin and enable the controller. alternatively, the run pin may be externally pulled up or driven directly by logic. be careful not to exceed the absolute maximum rating of 6v on this pin. the start-up of the controllers output voltage, v out , is controlled by the voltage on the tk/ss pin, if the internal soft-start has expired. when the voltage on the tk/ss pin is less than the 0.6 v internal reference, the LTC7130 regulates the v fb voltage to the tk/ss pin voltage instead of the 0.6v reference. this allows the tk/ss pin to be used to program a soft-start by connecting an external capacitor from the tk/ss pin to sgnd. an internal 1.25 a pull-up current charges this capacitor, creating a voltage ramp on the tk/ss pin. as the tk/ss voltage rises linearly from 0v to 0.6v (and beyond), the output voltage, v out , rises smoothly from zero to its final value. alternatively, the tk/ ss pin can be used to cause the start-up of v out to track that of another supply. typically, this requires connect- ing to the tk/ss pin an external resistor divider from the other supply to ground ( see the applications information section). when the run pin is pulled low to disable the controller, or when intv cc drops below its undervoltage lockout threshold of 3.75 v, the tk/ss pin is pulled low by an internal mosfet. when in undervoltage lockout, the controller is disabled and the mosfets are held off. light load current operation (burst mode operation, pulse-skipping or continuous conduction) the LTC7130 can be enabled to enter high efficiency burst mode operation, constant - frequency pulse- skipping mode or forced continuous conduction mode. to select forced continuous operation, tie the mode/pllin pin to sgnd. to select pulse-skipping mode of operation, tie the mode/ pllin pin to intv cc . to select burst mode operation, float the mode/pllin pin. when the controller is enabled for burst mode operation, the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the ith pin indicates a lower value. if the average inductor current is higher than the load current, the error amplifier, ea, will decrease the voltage on the ith pin. when the ith voltage drops below 0.5v, the internal sleep signal goes high (enabling sleep mode) and both mosfets are turned off. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the ea s output begins to rise. when the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top mosfet on the next cycle of the internal oscillator. when the controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator (i rev ) turns off the bottom mosfet just before the inductor current reaches zero, preventing it from reversing and going negative. thus, the controller operates in discontinuous operation. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the ith pin, just as in normal operation. in this mode, the efficiency at light loads is lower than in burst mode operation. however, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. when the mode/pllin pin is connected to intv cc , the LTC7130 operates in pwm pulse skipping mode at light loads. at very light loads, the current comparator, i cmp , may remain tripped for several cycles and force the top mosfet to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse ( discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current efficiency than forced continuous mode, but not nearly as high as burst mode operation. operation ltc 7130 7130fb
13 for more information www.linear.com/LTC7130 frequency selection and phase-locked loop (freq and mode/pllin pins) the selection of switching frequency is a trade- off between efficiency and component size. low frequency opera- tion increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. if the mode/pllin pin is not being driven by an external clock source, the freq pin can be used to program the controllers operating frequency from 250 khz to 770khz. there is a precision 10 a current flowing out of the freq pin so that the user can program the controllers switch - ing frequency with a single resistor to sgnd. a curve is provided later in the applications information section showing the relationship between the voltage on the freq pin and switching frequency. a phase-locked loop ( pll) is available on the LTC7130 to synchronize the internal oscillator to an external clock source that is connected to the mode/pllin pin. the pll loop filter network is integrated inside the LTC7130. the phase - locked loop is capable of locking any frequency within the range of 250khz to 770 khz. the frequency setting resistor should always be present to set the controllers initial switching frequency before locking to the external clock. the controller operates in forced continuous mode when it is synchronized. sensing the output voltage with a differential amplifier the LTC7130 includes a low offset, high input impedance, unity-gain, high bandwidth differential amplifier for ap - plications that require true remote sensing. sensing the load across the load capacitors directly greatly benefits regulation in high current, low voltage applications, where board interconnection losses can be a significant portion of the total error budget. connect diffp to the output load, and diffn to the load ground. see figure 1. the LTC7130 differential amplifier has a typical output slew rate of 2 v/s. the amplifier is configured for unity gain, meaning that the difference between diffp and diffn is translated to diffout, relative to sgnd. operation figure 1. differential amplifier connection diffout LTC7130 diffp c out v out diffn v fb 7130 f01 ? + diffamp care should be taken to route the diffp and diffn pcb traces parallel to each other all the way to the remote sensing points on the board. in addition, avoid routing these sensitive traces near any high speed switching nodes in the circuit. ideally, the diffp and diffn traces should be shielded by a low impedance ground plane to maintain signal integrity. the maximum output voltage is limited to 3.5 v when using the differential amplifier. if the differential amplifier is not used, tie the feedback divider directly across the output with its center point connected to v fb and ground the snsd + pin. in this case the maximum supported v out is 5v. power good (pgood pin) the pgood pin is connected to the open drain of an internal n-channel mosfet. the mosfet turns on and pulls the pgood pin low when the v fb pin voltage is not within 10% of the 0.6 v reference voltage. the pgood pin is also pulled low when the run pin is below 1.1 v or when the LTC7130 is in the soft-start or tracking up phase. when the v fb pin voltage is within the 10% regulation window, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6 v. the pgood pin will flag power good immediately when the v fb pin is within the regulation window. however , there is an internal 20 s power-bad mask when the v fb goes out of the window. inductor dcr sensing temperature compensation (itemp pin) inductor dcr current sensing provides a lossless method of sensing the instantaneous current. therefore, it can provide higher efficiency for applications with high output currents. however, the dcr of a copper inductor typically ltc 7130 7130fb
14 for more information www.linear.com/LTC7130 operation has a positive temperature coefficient. as the temperature of the inductor rises, its dcr value increases. the current limit of the controller is therefore reduced. the LTC7130 offers a method to counter this inaccuracy by allowing the user to place an ntc temperature sensing resistor near the inductor. a constant and precise 10a current flows out of the itemp pin. by connecting a linear - ized ntc resistor network from the itemp pin to sgnd, the maximum current sense threshold can be varied over temperature according to the following equation: v sensemax( adj) = v sense(max) 2.2 ? v itemp 1.5 where: v sensemax( adj) is the maximum adjusted current sense threshold. v sense(max) is the maximum current sense threshold specified in the electrical characteristics table. it is typi- cally 10mv , 15mv, 20mv , 25 mv or 30 mv, depending on the i lim pins voltage. v itemp is the voltage of the itemp pin. the valid voltage range for dcr temperature compensation on the itemp pin is between 0.7 v to sgnd with 0.7 v or above being no dcr temperature correction. an ntc resistor has a negative temperature coefficient, meaning that its resistance decreases as its temperature rises. the v itemp voltage, therefore, decreases as the induc - tor s t emperature i ncreases, and in turn the v sensemax ( adj ) will increase to compensate for the inductor s dcr temperature coefficient. the ntc resistor, however, is non-linear and the user can linearize its value by building a resistor network with regular resistors. output overvoltage protection an overvoltage comparator, ov, guards against transient overshoots (>10%) as well as other more serious condi - tions that may overvoltage the output. in such cases, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. undervoltage lockout the LTC7130 has two functions that help protect the controller in case of undervoltage conditions. a precision uvlo comparator constantly monitors the intv cc voltage to ensure that an adequate gate-drive voltage is present. it locks out the switching action when intv cc is below 3.75v. to prevent oscillation when there is a disturbance on the intv cc , the uvlo comparator has 500 mv of preci- sion hysteresis. another way to detect an undervoltage condition is to monitor the v in supply. because the run pin has a preci- sion turn -on reference of 1.22 v, one can use a resistor divider to v in to turn on the ic when v in is high enough. an extra 4.5 a of current flows out of the run pin once the run pin voltage passes 1.22 v. the run comparator itself has about 80 mv of hysteresis. one can program additional hysteresis for the run comparator by adjust - ing the values of the resistive divider. for accurate v in undervoltage detection, v in needs to be higher than 4.75v. ltc 7130 7130fb
15 for more information www.linear.com/LTC7130 the typical application on the first page of this data sheet is a basic LTC7130 application circuit. the LTC7130 is designed and optimized for use with a very low dcr value by utilizing a novel approach to reduce the noise sensitivity of the sensing signal by a factor of 14 db. dcr sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. however, as the dcr value drops below 1 m, the signal-to-noise ratio is low and current sensing is difficult. LTC7130 uses an lt c propri - etary technique to solve this issue. in general, external component selection is driven by the load requirement, and begins with the dcr and inductor value. next, input and output capacitors are selected. current limit programming the ilim pin is a 5- level logic input which sets the maxi - mum current limit of the controller. when ilim is either grounded, floated or tied to intv cc , the typical value for the maximum current sense threshold will be 10mv, 20mv or 30 mv, respectively. setting ilim to one-fourth intv cc and three-fourths intv cc for maximum current sense thresholds of 15mv and 25mv. which setting should be used? for the best current limit accuracy, use the highest setting that is applicable to the output requirements. snsd + , snsa + and sns C pins compared to the conventional dcr sensing where there are only 2 sense pins, sense + and sense C to sense across the dcr value of an inductor, the LTC7130 is designed to sense very low dcr value inductors in the sub milli- ohms range by adding an extra current sensing loop with snsd + pin. the snsa + and sns C pins are the inputs to the current comparators, while the snsd + pin is the input of an internal amplifier. all the positive sense pins that are connected to the cur - rent comparator or the amplifier are high impedance with input bias currents of less than 1 a, but there is also a resistance of about 300 k from the sns C pin to ground. the sns C should be connected directly to vout. the snsd + pin connects to the filter that has a r 1 ? c1 time constant matched to l/dcr of the inductor. the snsa + pin is con- nected to the second filter with the time constant one-fifth that of r 1 ? c1. care must be taken not to float these pins during normal operation. filter components, especially capacitors, must be placed close to the LTC7130, and the sense lines should run close together to a kelvin con - nection underneath the current sense element ( figure?2). because the LTC7130 is designed to be used with a very low dcr value to sense inductor current, without proper care, the parasitic resistance, capacitance and inductance will degrade the current sense signal integrity, making the programmed current limit unpredictable. as shown in figure 3, resistors r1 and r2 are placed close to the inductor and capacitors c1 and c2 are close to the ic pins to prevent noise coupling to the sense signal. when the snsd + pin is in use for low dcr sensing, the maximum output voltage allowed is 3.5 v due to the limita- tion of the internal amplifiers inputs operating range. if low dcr sensing is not needed, the LTC7130 could also be used like any typical current mode controller by disabling the snsd + pin, shorting it to ground. rc filter can be used to sense the output inductor signal and connects to the snsa + pin. its time constant, r ? c, is equaled to l/dcr of the output inductor. in these applications, the current limit, v sense(max) , will be five times larger for the specified i lim , and the operating voltage range of snsa + and sns C is from 0 v to 5 v. without using the internal differential amplifier, the output voltage of 5 v can be generated as shown in the typical application section. figure 2. sense lines placement with inductor dcr c out to sense filter, next to the controller inductor 7130 f02 applications information ltc 7130 7130fb
16 for more information www.linear.com/LTC7130 applications information inductor dcr sensing the LTC7130 is specifically designed for high load current applications requiring the highest possible efficiency; it is capable of sensing the signal of an inductor dcr in the sub milliohm range (figure 3). the dcr is the dc winding resistance of the inductor s copper, which is often less than 1m for high current inductors. in high current and low output voltage applications, a conduction loss of a high dcr or a sense resistor will cause a significant reduction in power efficiency. for a specific output requirement, chose the inductor with the dcr that satisfies the maxi - mum desirable sense voltage, and uses the relationship of the sense pin filters to output inductor characteristics as depicted below. dcr = v sense(max) i max + ? i l 2 l/dcr = r 1 ? c 1 = 5 ? r 2 ? c 2 where: v sense(max) : maximum sense voltage for a given i lim threshold i max : maximum load current ?i l : inductor ripple current l, dcr: output inductor characteristics r1, c1: filter time constant of the snsd + pin r2, c2: filter time constant of the snsa + pin to ensure that the load current will be delivered over the full operating temperature range, the temperature coefficient of dcr resistance, approximately 0.4%/ c, should be taken into account. the LTC7130 features a dcr temperature compensation circuit that uses an ntc temperature sensing resistor for this purpose. see the inductor dcr sensing temperature compensation section for details. typically, c1 and c2 are selected in the range of 0.047 f to 0.47 f. if c1 and c2 are chosen to be 220 nf, and an inductor of 0.25 h with 0.37 m dcr is selected, r1 and r2 will be 3.09 k and 619 respectively. the bias current at snsd + and snsa + is about 30 na and 500 na respectively, and it causes some small error to the sense signal. there will be some power loss in r1 and r2 that relates to the duty cycle, and will be the most in continuous mode at the maximum input voltage: p loss r ( ) = v in(max) C v out ( ) ? v out r figure 3. inductor dcr current sensing v in sv in v in intv cc boost sw itemp r ntc 100k inductor dcrl snsd + snsa + sns ? sgnd gnd LTC7130 v out 7130 f03 r1 c1 c2 place c1, c2 next to ic place r1, r2 next to inductor r1c1 = 5 r2c2 r s 20k r itemp r p 100k r2 ltc 7130 7130fb
17 for more information www.linear.com/LTC7130 applications information ensure that r1 and r2 have a power rating higher than this value. however, dcr sensing eliminates the conduction loss of a sense resistor; it will provide a better efficiency at heavy loads. the actual ripple voltage will be determined by the following equation: ? v sense = v out v in ? v in C v out r1? c1? f osc inductor dcr sensing temperature compensation with ntc thermistor for dcr sensing applications, the temperature coefficient of the inductor winding resistance should be taken into account when the accuracy of the current limit is critical over a wide range of temperature. the main element used in inductors is copper; that has a positive tempco of ap - proximately 4000ppm/c . the LTC7130 provides a feature to correct for this variation through the use of the itemp pin. there is a 10 a precision current source flowing out of the itemp pin. a thermistor with a ntc ( negative tem - perature coefficient ) resistance can be used in a network, r itemp (figure 3) connected to maintain the current limit threshold constant over a wide operating temperature. the itemp voltage range that activates the correction is from 0.7 v or less. if floating this pin, its voltage will be at intv cc potential, about 5.5 v. when the itemp voltage is higher than 0.7v , the temperature compensation is inactive. the following guidelines will help to choose components for temperature correction. the initial compensation is for 25c ambient temperature: 1. set the itemp pin resistance to 70 k at 25 c. with 10a flowing out of the itemp pin, the voltage on the itemp pin will be 0.7 v at room temperature. current limit correction will occur for inductor temperatures greater than 25c. 2. calculate the itemp pin resistance at the maximum inductor temperature, which is typically 100c. use the following equations: v itemp100c = 0.7 ? 1.5 i max dcr (max) 100 c ? 25 c ( ) 0.4 100 v sense(max) ? ? ? ? ? ? ? ? ? ? = 0.25v since v sense(max) = i max ? dcr (max): r itemp100c = v itemp100c 10a = 25k where: r itemp100c = itemp pin resistance at 100c; v itemp100c = itemp pin voltage at 100c; v sense(max) = maximum current sense threshold at room temperature; i max = maximum load current; and dcr (max) = maximum dcr value. calculate the values for the ntc networks parallel and series resistors, r p and r s . a simple method is to graph the following r s versus r p equations with r s on the y-axis and r p on the x-axis. r s = r itemp25c C r ntc25c ||r p r s = r itemp100c C r ntc100c ||r p next, find the value of r p that satisfies both equations, which will be the point where the curves intersect. once r p is known, solve for r s . the resistance of the ntc thermistor can be obtained from the vendors data sheet in the form of graphs, tabulated data, or formulas. the approximate value for the ntc thermistor for a given temperature can be calculated from the following equation: r = r o ? exp b ? 1 t + 273 C 1 t o + 273 ? ? ? ? ? ? ? ? ? ? ? ? ltc 7130 7130fb
18 for more information www.linear.com/LTC7130 applications information where: r = resistance at temperature t, which is in degrees c. r o = resistance at temperature t o , typically 25c. b = b-constant of the thermistor. figure 4 shows a typical resistance curve for a 100k thermistor and the itemp pin network over temperature. v itemp = 10a ? (r s + r p ||r ntc ); i dc(max) = maximum average inductor current; and t l is the inductor temperature. the resulting current limit should be greater than or equal to i max for inductor temperatures between 25 c and 100 c. with the front page circuit where the current limit setting is 15 mv, and inductor dcr is 0.37 m?, the LTC7130 can deliver 20 a of load current from 25 c to 125 c without the need for temperature compensation, however, if another inductor with a higher dcr is chosen, say 0.53 m?, the current limit can be compensated by using the temperature compensation network. (figure 5). figure 5. worst-case i max versus inductor temperature curve with and without ntc temperature compensation figure 6. thermistor location. place the thermistor next to the inductor for accurate sensing of the inductor temperature, but keep the itemp pin away from the switch nodes and gate drive traces v out r ntc l1 sw1 7130 f06 figure 4. resistance versus temperature for the itemp pin network and the 100k ntc starting values for the ntc compensation network are: ? ntc r o = 100k ? r s = 20k ? r p =100k but, the final values should be calculated using the above equations and checked at 25 c and 100 c. after determin - ing the components for the temperature compensation network, check the results by plotting i max versus inductor temperature using the following equations: i dc(max) = v sensemax(adj) ? v sense 2 dcr(max) at 25 c 1 + t l(max) ? 25 c ( ) 0.4 100 ? ? ? ? ? ? where: v sensemax(adj) = v sense(max) 2.2 ? v itemp 1.5 ; ltc 7130 7130fb ?25 0 25 50 75 100 125 1 10 100 thermistor resistance 1k 10k resistance () 7130 f04 dcr = 0.53m l = 0.33h ritemp: r s = 20k r p = 100k thermistor: r o = 100k, t o = 25c r o = 100k t o = 25c b = 4334 for 25c to 125c nominal i max uncorrected i max corrected i max inductor temperature (c) ?50 ?25 0 b = 4334 for 25c to 100c 25 50 75 100 125 150 10 12 14 16 ritemp 18 20 22 24 26 28 30 i max (a) 7130 f05 r s = 20k r p = 100k temperature (c) ?50
19 for more information www.linear.com/LTC7130 for the most accurate temperature detection, place the thermistor next to the output inductor as shown in figure ?6 . care should be taken to keep the itemp sense line away from switch nodes. pre-biased output start-up there may be situations that require the power supply to start up with a pre-bias on the output capacitors. in this case, it is desirable to start up without discharging that output pre-bias. the LTC7130 can safely power up into a pre-biased output without discharging it. the LTC7130 accomplishes this by turning off both top and bottom mosfets until the tk/ss pin voltage and the internal soft-start voltage are above the v fb pin voltage. when v fb is higher than tk/ss or the internal soft-start voltage, the error amp output is railed low. the control loop would like to turn bottom mosfet on, which would discharge the output. disabling both mosfets will prevent the pre-biased output voltage from being discharged. when tk/ss and the internal soft-start both cross 500mv or v fb , whichever is lower, both mosfets are enabled. if the pre-bias is higher than the ov threshold, the bottom mosfet is turned on immediately to pull the output back into the regulation window. overcurrent fault recovery when the output of the power supply is loaded beyond its preset current limit, the regulated output voltage will collapse depending on the load. the output may be shorted to ground through a very low impedance path or it may be a resistive short, in which case the output will collapse partially, until the load current equals the preset current limit. the controller will continue to source current into the short. the amount of current sourced depends on the ilim pin setting and the v fb voltage as shown in the current foldback graph in the typical performance characteristics section. upon removal of the short, the output soft starts using the internal soft-start, thus reducing output overshoot. in the absence of this feature, the output capacitors would have been charged at current limit, and in applications with minimal output capacitance this may have resulted in output overshoot. current limit foldback is not disabled during an overcurrent recovery. the load must step below the folded back current limit threshold in order to restart from a hard short. thermal considerations in some applications where the LTC7130 is operated at high ambient temperature, high v in , high switching frequency and maximum output current load, the heat dissipated may exceed the maximum junction temperature of the part. to avoid the LTC7130 from exceeding the maximum junction temperature, current rating shall be derated in accordance to ambient temperature vs maximum load current in the typical performance characteristics. the junction to ambient thermal resistance will vary depending on the size amount of heat sinking copper on the pcb board where the part is mounted, as well as the amount of air flow on the device. figure 7, 8 and 9 show temperature derating with both heatsink and airflow. applications information figure 7. temperature derating curve based on the dc2341a demo board ltc 7130 7130fb 0 25 50 75 100 125 0 5 10 15 v out = 1.5v 20 25 maximum load current (a) thermal derating vin = 5v 7130 g07 v in = 5v f sw = 500khz dc2341a demo board with heat sink 0lfm 200lfm 400lfm ambient temperature (c)
20 for more information www.linear.com/LTC7130 tables 1 and 2 provide heat sink and thermal conductive adhesive tape information. table 1. heat sink manufacturer (thermally conductive adhesive tape pre-attached) heat sink manufacturer part number website cool innovations 3-040404u www.coolinnovations.com table 2. thermally conductive adhesive tape vendor thermally conductive adhesive tape manufacturer part number website chomerics t411 www.chomerics.com inductor value calculation given the desired input and output voltages, the inductor value and operating frequency, f osc , directly determine the inductors peak-to-peak ripple current: i ripple = v out v in v in C v out f osc ? l ? ? ? ? ? ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors, and output voltage ripple. thus, highest efficiency operation is obtained at low frequency with a small ripple current. achieving this, however, requires a large inductor. it is recommended to choose a ripple current that is about 50% of i out(max) . note that the largest ripple current oc- curs at the highest input voltage. to guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: l v in C v out f osc ?i ripple ? v out v in inductor core selection once the inductance value is determined, the type of in- ductor must be selected. core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con - centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! c in and c out selection in continuous mode, the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the applications information figure 8. temperature derating curve based on the dc2341a demo board figure 9. temperature derating curve based on the dc2341a demo board ltc 7130 7130fb ambient temperature (c) 0 25 50 75 100 125 0 5 10 v out = 1.5v 15 20 25 maximum load current (a) thermal derating vin = 12v 7130 f08 v out = 1.5v f sw = 500khz dc2341a demo board with heat sink v in = 12v 0lfm 200lfm 400lfm ambient temperature (c) 0 25 50 75 100 125 f sw = 500khz 0 5 10 15 20 25 maximum load current (a) thermal derating vin = 20v 7130 f09 v in = 20v dc2341a demo board with heat sink 0lfm 200lfm 400lfm
21 for more information www.linear.com/LTC7130 maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c in required i rms i max v in v out ( ) v in C v out ( ) ? ? ? ? 1/2 this formula has a maximum at v in = 2v out , where i rms ?=?i out /2. this simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capaci - tor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the LTC7130, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. ceramic capacitors are becoming very popular for small designs but several cautions should be observed . x7r , x5r and y5v are examples of a few of the ceramic materials used as the dielectric layer, and these different dielectrics have very different effect on the capacitance value due to the voltage and temperature conditions applied. physically , if the capacitance value changes due to applied voltage change, there is a concomitant piezo effect which results in radiating sound ! a load that draws varying current at an audible rate may cause an attendant varying input volt- age on a ceramic capacitor, resulting in an audible signal. a secondar y issue relates to the energy flowing back into a ceramic capacitor whose capacitance value is being reduced by the increasing charge. the voltage can increase at a considerably higher rate than the constant current being supplied because the capacitance value is decreasing as the voltage is increasing! nevertheless, ceramic capacitors, when properly selected and used, can provide the lowest overall loss due to their extremely low esr. a small (0.1 f to 1 f) bypass capacitor, c in , between the chip v in pin and ground, placed close to the LTC7130, is also suggested. a 2.2 to 10 resistor placed between c in and v in pin provides further isolation. the selection of c out is driven by the required effective series resistance ( esr). typically once the esr require- ment is satisfied the capacitance is adequate for filtering. the steady-state output ripple (?v out ) is determined by: ? v out ? i ripple esr + 1 8fc out ? ? ? ? ? ? where f = operating frequency, c out = output capacitance and ?i ripple = ripple current in the inductor. the output ripple is highest at maximum input voltage since ?i ripple increases with input voltage. the output ripple will be less than 50 mv at maximum v in with ?i ripple = 0.4 i out(max) assuming: c out required esr < n ? r sense and c out > 1 8f ( ) r sense ( ) the emergence of very low esr capacitors in small, surface mount packages makes very small physical implementa- tions possible . the ability to externally compensate the switching regulator loop using the ith pin allows a much wider selection of output capacitor types. the impedance characteristic of each capacitor type is significantly differ - ent than an ideal capacitor and therefore requires accurate modeling or bench evaluation during design. manufacturers such as nichicon, nippon chemi- con and sanyo should be considered for high performance through- hole capacitors. the os- con semiconductor dielectric capacitors available from sanyo and the panasonic sp surface mount types have a good (esr)(size) product. once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple (p-p) require- ment. ceramic capacitors from avx , taiyo yuden, murata and tdk offer high capacitance value and very low esr, especially applicable for low output voltage applications. in surface mount applications, multiple capacitors may have to be paralleled to meet the esr or rms current handling requirements of the application. aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. new special polymer surface mount capacitors offer very low esr also but have much lower capacitive density per unit volume. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. several applications information ltc 7130 7130fb
22 for more information www.linear.com/LTC7130 applications information excellent choices are the avx tps, avx tpsv, the kemet t510 series of surface mount tantalums or the panasonic sp series of surface mount special polymer capacitors available in case heights ranging from 2 mm to 4 mm. other capacitor types include sanyo poscap, sanyo os-con, nichicon pl series and sprague 595 d series. consult the manufacturers for other specific recommendations. differential amplifier the LTC7130 has true remote voltage sense capability. the sense connections should be returned from the load, back to the differential amplifiers inputs through a com - mon, tightly coupled pair of pc traces. the differential amplifier rejects common mode signals capacitively or inductively radiated into the feedback pc traces as well as ground loop disturbances. the LTC7130 diffamp has 80k input impedance on diffp. it is designed to be con - nected directly to the output. the output of the diffamp connects to the v fb pin through a voltage divider, setting the output voltage. external soft-start and tracking the LTC7130 has the ability to either soft-start by itself or track the output of another channel or external supply. when the controller is configured to soft-start by itself, a capacitor may be connected to its tk/ss pin or the internal soft-start may be used. the controller is in the shutdown state if its run pin voltage is below 1.1 v and its tk/ss pin is actively pulled to ground in this shutdown state. if the run pin voltage is above 1.22 v, the controller powers up. a soft-start current of 1.25 a then starts to charge the tk/ss soft-start capacitor. note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp volt - age according to the ramp rate on the tk/ss pin. current foldback is disabled during this phase to ensure smooth soft-start or tracking. the soft-start or tracking range is defined to be the voltage range from 0 v to 0.6 v on the tk/ss pin. the total soft-start time can be calculated as: t softstart = 0.6 ? c ss 1.25a regardless of the mode selected by the mode/pllin pin, the controller always starts in discontinuous mode up to tk/ss = 0.5 v. between tk/ss = 0.5 v and 0.54 v, it will operate in forced continuous mode and revert to the selected mode once tk/ss > 0.54 v. the output ripple is minimized during the 40 mv forced continuous mode window, ensuring a clean pgood signal. when the chan - nel is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the tk/ss pin. therefore, the volt - age ramp rate on this pin is determined by the ramp rate of the other supplys voltage. it is only possible to track another supply that is slower than the internal soft-start ramp. note that the small soft-start capacitor charging current is always flowing, producing a small offset error. to minimize this error, select the tracking resistive divider value to be small enough to make this error negligible. in order to track down another channel or supply after the soft-start phase expires, the LTC7130 is forced into continuous mode of operation as soon as v fb is below the undervoltage threshold of 0.54 v regardless of the setting on the mode/pllin pin. however, the LTC7130 should always be set in forced continuous mode tracking down when there is no load. after tk/ss drops below 0.1 v, the controller operates in discontinuous mode. the LTC7130 allows the user to program how its output ramps up and down by means of the tk/ss pin. through these pins, the output can be set up to either coinciden - tally or ratiometrically track another supplys output, as shown in figure 10. in the following discussions, v out2 refers to the LTC7130s output as a slave and v out1 refers to another supply output as a master. to implement the coincident tracking in figure 10 a, connect an additional resistive divider to v out1 and connect its mid-point to the tk/ss pin of the slave controller. the ratio of this divider should be the same as that of the slave controllers feed - back divider shown in figure 11 a. in this tracking mode, v out1 must be set higher than v out2 . to implement the ratiometric tracking in figure 10 b, the ratio of the v out2 divider should be exactly the same as the master control- lers feedback divider shown in figure 11b . by selecting different resistors, the LTC7130 can achieve different modes of tracking including the two in figure 10. ltc 7130 7130fb
23 for more information www.linear.com/LTC7130 figure 10. tw o different modes of output voltage tracking figure 11. setup and coincident and ratiometric tracking applications information so which mode should be programmed? while either mode in figure 10 satisfies most practical applications, some trade-offs exist. the ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. under ratiometric tracking, when the master controllers output experiences dynamic excursion (under load transient, for example), the slave controller output will be affected as well. for better output regulation, use the coincident tracking mode instead of ratiometric. intv cc (ldo) and extv cc the LTC7130 features a true pmos ldo that supplies power to intv cc from the v in supply. intv cc powers the gate drivers and much of the LTC7130s internal circuitry. the ldo regulates the voltage at the intv cc pin to 5.5v when v in is greater than 6 v. extv cc connects to intv cc through a p-channel mosfet and can supply the needed power when its voltage is higher than 4.7 v. either of these can supply a peak current of 100 ma and must be bypassed to ground with a minimum of 4.7 f ceramic capacitor or low esr electrolytic capacitor. no matter what type of bulk capacitor is used, an additional 0.1 f ceramic capacitor placed directly adjacent to the intv cc and pgnd pins is highly recommended. good bypassing is needed to sup- ply the high transient currents required by the mosfet gate drivers. high input voltage applications in which the internal mosfets are being driven at high frequencies may cause the maximum junction temperature rating for the LTC7130 to be exceeded. the intv cc current, which is dominated by the gate charge current, also known as the driver current, may be supplied by either the 5.5 v ldo or extv cc . when the voltage on the extv cc pin is less than 4.5 v, the ldo is enabled. the gate charge current is dependent on operating frequency as discussed on ef - ficiency considerations section. the power dissipation for the ic in this case is equal to v in ? intv cc . for example, the LTC7130 intv cc current is about 27.5 ma from a 20v supply in the bga package not using the extv cc : p d = 20v ? 27.5ma = 0.55w time (10a) coincident tracking v out1 v out2 output voltage v out1 v out2 time 7130 f08 (10b) ratiometric tracking output voltage r3 r1 r4 r2 r3 v out2 r4 (11a) coincident tracking setup to v fb1 pin to tk/ss2 pin to v fb2 pin v out1 r1 r2 r3 v out2 r4 7130 f09 (11b) ratiometric tracking setup to v fb1 pin to tk/ss2 pin to v fb2 pin v out1 ltc 7130 7130fb
24 for more information www.linear.com/LTC7130 applications information to reduce the total power loss and prevent the maximum junction temperature from being exceeded due to the ic, the extv cc pin can be used to provide mosfet gate drive and control power. when the voltage applied to extv cc rises above 4.7 v, the intv cc ldo is turned off and the extv cc is connected to the intv cc . the extv cc remains on as long as the voltage applied to extv cc remains above 4.5v. using the extv cc allows the mosfet driver and control power to be derived from an efficient switching regulator output during normal operation. if more cur - rent is required through the extv cc than is specified, an external schottky diode can be added between the extv cc and intv cc pins. do not apply more than 6 v to the extv cc pin and make sure that extv cc < v in . significant efficiency and thermal gains can be realized by powering intv cc from extv cc , since the v in current resulting from the driver and control currents will be scaled by a factor of ( duty cycle)/(switcher efficiency). tying the extv cc pin to a 5 v supply reduces power loss of the ic to: p d = 5v ? 24.5ma = 0.14w however, for low voltage outputs, additional circuitry is required to derive intv cc power from the output. the following list summarizes the three possible connec- tions for extv cc : 1. extv cc grounded. this will cause intv cc to be pow- ered from the internal ldo resulting in an efficiency penalty of up to 10% at high input voltages. 2. extv cc connected to an external supply. if a 5 v external supply is available, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. 3. extv cc connected to an output-derived boost network. for 3.3 v and other low voltage regulators, efficiency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v. for applications where the main input power is 5 v, tie the v in and intv cc pins together and tie the combined pins to the 5 v input with a 1 or 2.2 resistor as shown in figure 12 to minimize the voltage drop caused by the gate charge current. this will override the intv cc linear regulator and will prevent intv cc from dropping too low due to the dropout voltage. make sure the intv cc voltage is at or exceeds the r ds(on) test voltage for the mosfet which is typically 4.5v for logic-level devices. figure 12. setup for a 5v input r vin 1 c in 7130 f12 5v c intvcc 4.7f + intv cc LTC7130 v in topside mosfet driver supply (c b , d b ) external bootstrap capacitor, c b , connected to the boost pin supplies the gate drive voltages for the topside mos- fet. capacitor c b in the functional diagram is charged through external diode d b from intv cc when the sw pin is low. when the topside mosfet is to be turned on, the driver places the c b voltage across the gate source of the mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc C v db the value of the boost capacitor, c b , needs to store approximately 100 times the gate charge required by the topside mosfet(s). the reverse breakdown of the external schottky diode must be greater than v in(max) . when adjusting the gate drive level, the final arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the efficiency has improved. if there is no change in input current, then there is no change in efficiency. for applications that require high v in and high output current, in order to minimize sw node?ringing and emi, connect a 2 ? to 10 ? resistor r boost in series with the boost pin. make the c b and d b connections on the other side of the resistor. this series resistor helps to ltc 7130 7130fb
25 for more information www.linear.com/LTC7130 figure 14. setting output voltage LTC7130 v fb diffout r b c ff r a 7130 f14 applications information slow down the sw node rise time, limiting the high d l / d t current through the top mosfet that causes sw node ringing (see figure 13). maximum sense voltage is progressively lowered from its maximum programmed value to one-third of the maxi - mum value . foldback current limiting is disabled during the soft-start or tracking up using the tk/ss pin. it is not disabled for internal soft-start. under short-circuit condi - tions with very low duty cycles, the LTC7130 will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short circuit ripple current is determined by the minimum on- time t on( min) of the LTC7130 (90 ns), the input voltage and inductor value: ? i l(sc) = t on(min) ? v in l the resulting short-circuit current is: i sc = 1/3 v sense(max) r sense C 1 2 ? i l sc ( ) ? ? ? ? ? ? after a short, or while starting with internal soft- start, make sure that the load current takes the folded-back current limit into account. phase-locked loop and frequency synchronization the LTC7130 has a phase-locked loop ( pll) comprised of an internal voltage-controlled oscillator ( vco) and a phase detector. this allows the turn-on of the top mosfet to be locked to the rising edge of an external clock signal applied to the mode/pllin pin. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complemen - tary current sources that charge or discharge the internal filter network. there is a precision 10 a current flowing out of the freq pin. this allows the user to use a single resistor to sgnd to set the switching frequency when no external clock is applied to the mode/pllin pin. the internal switch between the freq pin and the integrated pll filter network is on, allowing the filter network to be pre-charged to the same voltage as the freq pin. the figure 13. using boost resistor LTC7130 boost intv cc c bb 7130 f13 d b r boost sw setting output voltage the LTC7130 output voltage is set by an external feedback resistive divider carefully placed across the diffout pin, as shown in figure 14. the regulated output voltage is determined by: v out = 0.6v ? 1 + r b r a ? ? ? ? ? ? to improve the frequency response, a feedforward ca- pacitor, c ff , may be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. to minimize the effect of the voltage drop caused by high current flowing through board conductance; connect diffn and diffp sense lines close to the ground and the load output respectively. fault conditions: current limit and current foldback the LTC7130 includes current foldback to help limit load current when the output is shorted to ground. if the out - put falls below 50% of its nominal output level, then the ltc 7130 7130fb
26 for more information www.linear.com/LTC7130 applications information relationship between the voltage on the freq pin and operating frequency is shown in figure 15 and specified in the electrical characteristics table. if an external clock is detected on the mode/pllin pin, the internal switch mentioned above turns off and isolates the influence of the freq pin. note that the LTC7130 can only be synchronized to an external clock whose frequency is within range of the LTC7130s internal vco. this is guaranteed to be between 250 khz and 770 khz. a simplified block diagram is shown in figure 16. if the external clock frequency is greater than the inter - nal oscillator s frequency, f osc , then current is sourced continuously from the phase detector output, pulling up the filter network. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the filter network. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage on the filter network is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the filter capacitor c lp holds the voltage. typically, the external clock ( on the mode/ pllin pin) input high threshold is 1.6 v, while the input low threshold is 1v. minimum on-time considerations minimum on-time, t on(min) , is the smallest time duration that the LTC7130 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min) < v out v in f ( ) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the voltage ripple and current ripple will increase. the minimum on-time for the LTC7130 is approximately 90ns, with good pcb layout, minimum 50% inductor current ripple and at least 2 mv ripple on the current sense signal. the minimum on-time can be affected by pcb switch - ing noise in the voltage and current loop. as the peak sense voltage decreases the minimum on-time gradually increases to about 110 ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine figure 15. relationship between oscillator frequency and voltage at the freq pin figure 16. phase-locked loop block diagram freq pin voltage (v) 0 frequency (khz) 0.5 1 1.5 2 7130 f15 2.5 0 100 300 400 500 900 800 700 200 600 digital phase/ frequency detector vco 2.4v 5.5v 10a r set 7130 f16 freq sync external oscillator mode/pllin ltc 7130 7130fb
27 for more information www.linear.com/LTC7130 what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: % efficiency = 100%C(l1 + l2 + l3 +) where l1, l2, etc. are the individual losses as a per cent - age of input power. although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in LTC7130 circuits : 1) i 2 r losses , 2) switching and biasing losses, 3) other losses. 1. i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current flows through inductor l but is chopped between the internal top and bottom power mosfets. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on) top)(dc) + (r ds(on) bot)(1-dc) the r ds( on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus to obtain i 2 r losses: i 2 r losses = i out 2 (r sw + r l ) 2. the intv cc current is the sum of the power mosfet driver and control currents . the power mosfet driver current results from switching the gate capacitance of the power mosfets. each time a power mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the dc control bias current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the internal top and bottom power mosfets and f is the switching frequency. since intv cc is a low dropout regulator output powered by v in , its power loss equals: p ldo = v in ? i intvcc 3. other hidden losses such as transition loss and cop- per trace and internal load resistances can account for additional efficiency degradations in the overall power system. it is very important to include these system level losses in the design of a system. transi - tion loss arises from the brief amount of time the top power mosfet spends in the saturated region during switch node transitions. other losses including diode conduction losses during dead-time and inductor core losses which generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ?i load ? esr, where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out , generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the ith pin not only allows optimization of control loop behavior but also provides a dc-coupled and ac-filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed-loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examin - ing the rise time at the pin. the ith external components shown in the typical application circuit will provide an adequate starting point for most applications. the ith series r c -c c filter sets the dominant pole- zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a applications information ltc 7130 7130fb
28 for more information www.linear.com/LTC7130 rise time of 1 s to 10 s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the ith pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10 f capacitor would require a 250 s rise time, limiting the charging current to about 200ma. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 17. check the following in the pc layout: 1. the intv cc decoupling capacitor should be placed immediately adjacent to the ic between the intv cc pin and pgnd plane. a 1 f ceramic capacitor of the x7r or x5r type is small enough to fit very close to the ic to minimize the ill effects of the large current pulses drawn to drive the bottom mosfets. an additional 4.7f to 10 f of ceramic, tantalum or other very low esr capacitance is recommended in order to keep the internal ic supply quiet. 2. place the feedback divider between the + and C termi - nals of c out . route diffp and diffn with minimum pc trace spacing from the ic to the feedback divider. 3. are the snsd + , snsa + and sns C printed circuit traces routed together with minimum pc trace spacing? the filter capacitors between snsd + , snsa + and sns C should be as close as possible to the pins of the ic. connect the snsd + and snsa + pins to the filter resistors as illustrated in figure 3. applications information figure 17. branch current waveforms + r in v in v out c in + c out d1 sw2 sw1 l1 dcr r l 7130 f17 bold lines indicate high, switching currents. keep lines to a minimum length ltc 7130 7130fb
29 for more information www.linear.com/LTC7130 4. do the (+) plates of c in connect to the drain of the topside mosfet as closely as possible? this capacitor provides the pulsed current to the mosfet. 5. keep the switching nodes, sw, boost away from sensi - tive small -signal nodes (snsd + , snsa + , sns C , diffp, diffn, v fb ). ideally the sw, and boost printed circuit traces should be routed away and separated from the ic and especially the quiet side of the ic. separate the high d v /d t traces from sensitive small-signal nodes with ground traces or ground planes. 6. use a low impedance source such as a logic gate to drive the mode/pllin pin and keep the lead as short as possible. 7. the 47 pf to 330 pf ceramic capacitor between the i th pin and signal ground should be placed as close as possible to the ic. figure 17 illustrates all branch cur - rents in a switching regulator. it becomes very clear after studying the current waveforms why it is critical to keep the high switching current paths to a small physical size. high electric and magnetic fields will radiate from these loops just as radio stations transmit signals. the output capacitor ground should return to the negative terminal of the input capacitor and not share a com- mon ground path with any switched current paths. the left half of the circuit gives rise to the noise generated by a switching regulator. the gnd terminations and schottky diode should return to the bottom plate(s) of the input capacitor(s) with a short isolated pc trace since very high switched currents are present. external opti-loop ? compensation allows overcompensation for pc layouts which are not optimized but this is not the recommended design procedure. 8. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out (C) terminals. the v fb and ith traces should be as short as possible. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. applications information 9. use a modified star ground technique: a low imped- ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic. design example as a design example of the front page circuit for a single channel high current regulator, assume v in = 12 v( nominal), v in = 20 v(maximum), v out = 1.5 v, i max = 20 a, and f = 500khz (see front page schematic). the regulated output voltage is determined by: v out = 0.6v ? 1 + r b r a ? ? ? ? ? ? using a 20k 1% resistor from the v fb node to ground, the top feedback resistor is ( to the nearest 1% standard value) 30.1k. the frequency is set by biasing the freq pin to 1.2v (see figure 15). the inductance value is based on a 50% maximum ripple current assumption (10 a). the highest value of ripple current occurs at the maximum input voltage: l = v out f ? ? i l(max) 1 ? v out v in(max) ? ? ? ? ? ? ? ? this design will require 0.25 h. the wrth 744308025, 0.25h inductor is chosen. at the nominal input voltage (12v), the ripple current will be: ? i l(nom) = v out f ? l 1 ? v out v in(nom) ? ? ? ? ? ? ? ? it will have 10.5a (52.5%) ripple. the peak inductor cur- rent will be the maximum dc value plus one-half the ripple current, or around 25a. ltc 7130 7130fb
30 for more information www.linear.com/LTC7130 typical applications the minimum on-time occurs at the maximum v in , and should not be less than 90ns: t on(min) = v out v in(max) f = 1.5v 20v(500khz) = 150ns dcr sensing is used in this circuit. if c1 and c2 are chosen to be 220 nf, based on the chosen 0.25 h inductor with 0.37m dcr, r1 and r2 can be calculated as: r1 = l dcr ? c1 = 3.07k r2 = l dcr ? c2 ? 5 = 614 choose r1 = 3.09k and r2 = 619. the maximum dcr of the inductor is 0.4 m . the v sense(max) is calculated as: v sense(max) = 25a ? dcr max = 10mv the current limit is chosen to be 15 mv. if temperature variation is considered, please refer to inductor dcr sensing temperature compensation with ntc thermistor. for a 0.37 m dcr, a short-circuit to ground will result in a folded back current of: i sc = 1/ 3 ( ) 15mv 0.37m C 1 2 90ns(20v) 0.25h ? ? ? ? ? ? ? ? ? ? 10a c out is chosen with an equivalent esr of 4.5 m? for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr (?i l ) 0.0045? ? 10a = 45mv p-p further reductions in output voltage ripple can be made by placing a 100f ceramic capacitor across c out . very low output ripple converter although the LTC7130 recommends 50% inductor ripple for most its applications, for applications that need very small output ripple, the inductance can be increased to achieve smaller output ripple. the schematic as shown figure 18 is similar to that of the front page circuit, except that three times the inductance and double the output capacitance are used. the com - pensation components are changed to maintain the same crossover frequency and phase margin. figure 19 shows the transient response of 10 a load step, and figure?20 demonstrates that the output voltage ripple is a factor of six smaller than that of typical current mode converters. ltc 7130 7130fb
31 for more information www.linear.com/LTC7130 figure 18. high efficiency, 1.5v/15a step-down converter with very low output ripple figure 19. load step transient response figure 20. very low output voltage ripple typical applications 7130 f18 v out 1.5v 20a c out 470f 4 v in 5v to 20v 0.72h, dcr = 1.3m, 744325072 ltc 7130 7130fb 7130 f19 very low output voltage ripple 2s/div v out typical front page ac?coupled 10mv/div v out low ripple figure 18 ac?coupled v in = 12v 10mv/div 7130 f20 cmdsh3 4.7f 1f 220f 10f x2 220pf 0.1f i load = 1a to 10a 3.3nf extv cc pgood pins not used in this circuit: 20k 121k 30.1k 26.1k clkout 2.49k 20s/div 220nf 499 220nf 0.22f 2.2 intv cc tk/ss ith gnd sv in v out freq sns ? snsa + snsd + sw boost ilim diffn diffp mode/pllin ac?coupled diffout v fb itemp sgnd run v in LTC7130 100mv/div i load 5a/div
32 for more information www.linear.com/LTC7130 typical applications high efficiency, dual phase very low dcr sensing 1.2v/40a step-down supply v out 1.2v 40a c out 330f 2 v in 7v to 14v 0.25h, dcr = 0.37m, wurth 744308025 7130 ta03 10f 2 180f 2 100f 2 c out 330f 2 0.25h, dcr = 0.37m, wurth 744308025 10f 2 220f 100f 2 ltc 7130 7130fb u1 pins not used in this circuit: 20k 137k 20k 2.49k itemp 3.09k 220nf 619 220nf cmdsh3 0.22f 2.2 intv cc tk/ss ith run gnd sv in freq sns ? 4.7f snsa + snsd + sw boost diffn diffp mode/pllin diffout v fb pgood 1f clkout sgnd ilim v in u1 LTC7130 120k pgood ith tk/ss v fb 120pf run 1/4 v intv cc cmdsh3 4.7f 1f 120pf extv cc clkout u2 pins not used in this circuit: 137k 0.1f diffout itemp 3.09k 220nf 619 220nf 0.22f 2.2 intv cc tk/ss ith 3.3nf ilim gnd sv in mode/pllin freq sns ? snsa + snsd + sw boost extv cc diffn diffp v fb pgood sgnd run v in u2 LTC7130 pgood ith pgood tk/ss v fb 1/4 v intv cc run 1.8 1.8
33 for more information www.linear.com/LTC7130 package photographs ltc 7130 7130fb
34 for more information www.linear.com/LTC7130 package description please refer to http://www .linear.com/product/LTC7130#packaging for the most recent package drawings. notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 6. solder ball composition is 96.5% sn/3.0% ag/0.5% cu 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature package top view 4 pin ?a1? corner x y aaa z aaa z package bottom view 3 see notes suggested pcb layout top view bga 63 0914 rev ? ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? pin 1 0.000 0.80 0.80 1.60 1.60 2.40 2.40 3.20 0.80 2.40 1.60 0.80 1.60 2.40 3.20 0.000 detail a ?b (63 places) f h j e g a b c d 2 1 4 3 567 detail b substrate // bbb z d a a1 b1 ccc z detail b package side view mold cap z m x yzddd m zeee 0.4 0.025 ? 63x symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 2.07 0.35 1.72 0.45 0.37 0.27 1.45 nom 2.22 0.40 1.82 0.50 0.40 7.50 6.25 0.80 6.40 4.80 0.32 1.50 max 2.37 0.45 1.92 0.55 0.43 0.37 1.55 0.15 0.10 0.12 0.15 0.08 notes dimensions total number of balls: 63 e b e e b a2 f g bga package 63-lead (7.5mm 6.25mm 2.22mm) (reference ltc dwg # 05-08-1988 rev ?) h1 h2 7 package row and column labeling may vary among module products. review each package layout carefully ! 7 see notes detail a ltc 7130 7130fb
35 for more information www.linear.com/LTC7130 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 07/16 modified i q conditions changed run threshold value modified intv cc /extv cc section, added note 7 3 8, 12, 13, 22 11 b 05/17 corrected pin number of boost pin 8 ltc 7130 7130fb
36 for more information www.linear.com/LTC7130 ? linear technology corporation 2016 lt 0517 rev b ? printed in usa www.linear.com/LTC7130 related parts typical application 5v/5a step-down converter part number description comments ltc3605/ ltc3605a 20v, 5a synchronous step-down regulator 4v < v in < 20v, 0.6v < v out < 20v, 96% max efficiency, 4mm 4mm qfn-24 package ltc3633a ltc3633a-1 dual channel 3a, 20v monolithic synchronous step - down regulator 3.6v < v in < 20v, 0.6v < v out < v in , 95% max efficiency, 4mm 5mm qfn-28 and tssop-28 package ltc3622 17v, dual 1a synchronous step-down regulator with ultralow quiescent current 2.7v < v in < 17v, 0.6v < v out < v in , 95% max efficiency, 3mm 4mm dfn-14 and msop-16 package ltc3613 24v, 15a monolithic step-down regulator with differential output sensing 4.5v < v in < 24v, 0.6v < v out < 5.5v, 0.67% output voltage accuracy, valley current mode, programmable from 200khz to 1mhz, current sensing, 7mm 9mm qfn-56 package ltc3624 17v, 2a synchronous step-down regulator with 3.5a?quiescent current 2.7v < v in < 17v, 0.6v < v out < v in , 95% max efficiency, 3.5a i q , zero - current shutdown, 3mm 3mm dfn-8 package lt m ? 4639 low v in 20a dc/dc module ? step-down regulator complete 20 a switch mode power supply , 2.375v < v in < 7v, 0.6v ?LTC7130 pgood 120k 20k 180f x2 147k v fb cmdsh3 0.22f 2.2 10f x2 100pf 0.1f 2.2nf

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